ASIC Design Verification / Validation Engineer (Intermediate, Senior, Principal Levels)
Location
ahuntsic north, qc
Job Type
Full-time
Category
Engineering
Posted
May 31, 2026
ASIC Design Verification (block, subsystem, and full SoC levels) Strong
SystemVerilog + UVM/OVM
(testbench architecture, sequences, coverage) Develop
verification plans, test strategies, and coverage models
from specs Constrained random verification,
assertions, and functional coverage Debug complex issues using
waveform analysis and root-cause methodologies Experience with
large, complex SoCs (AI, GPU, HPC, networking) Integration and use of
3rd-party Verification IP (VIP) Perform
code coverage and functional coverage closure Strong RTL understanding ( Verilog/SystemVerilog ) for design validation Experience with
processor architectures
(ARM, MIPS, RISC-V) Familiarity with
AMBA protocols
(AXI, AHB, APB) and SoC interfaces Exposure to
high-speed interfaces
(PCIe, Ethernet, DDR, USB, SPI, I2C) Scripting for automation ( Python, Perl, Tcl, Bash ) Experien...
SystemVerilog + UVM/OVM
(testbench architecture, sequences, coverage) Develop
verification plans, test strategies, and coverage models
from specs Constrained random verification,
assertions, and functional coverage Debug complex issues using
waveform analysis and root-cause methodologies Experience with
large, complex SoCs (AI, GPU, HPC, networking) Integration and use of
3rd-party Verification IP (VIP) Perform
code coverage and functional coverage closure Strong RTL understanding ( Verilog/SystemVerilog ) for design validation Experience with
processor architectures
(ARM, MIPS, RISC-V) Familiarity with
AMBA protocols
(AXI, AHB, APB) and SoC interfaces Exposure to
high-speed interfaces
(PCIe, Ethernet, DDR, USB, SPI, I2C) Scripting for automation ( Python, Perl, Tcl, Bash ) Experien...