ASIC DFT Technical Lead
Location
San Jose, CA
Job Type
Full-time
Category
other-general
Posted
June 13, 2026
The application window is expected to close on: 07/03/2026
**Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received** .
**Meet the Team:**
You will be part of the Silicon One development organization as an ASIC implementation engineer in San Jose, CA. As a member of this team you will be involved in crafting cutting edge next generation networking chips.
**Your Impact:**
You will be the lead to drive the DFT/DFx and quality process through the early product life cycle: the architecture definitions, RTL implementation and quality checks. You will also be engaged in relevant development of flow/methodologies, test plans, tape-out sign-off requirements, post silicon validation, production yield & DPPM support.
**Key Responsibilities:**
+ Responsible for development of the comprehensive Design-for-Test (DFT) & DFx solutions and architectures that support ATE screening, in-s...
**Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received** .
**Meet the Team:**
You will be part of the Silicon One development organization as an ASIC implementation engineer in San Jose, CA. As a member of this team you will be involved in crafting cutting edge next generation networking chips.
**Your Impact:**
You will be the lead to drive the DFT/DFx and quality process through the early product life cycle: the architecture definitions, RTL implementation and quality checks. You will also be engaged in relevant development of flow/methodologies, test plans, tape-out sign-off requirements, post silicon validation, production yield & DPPM support.
**Key Responsibilities:**
+ Responsible for development of the comprehensive Design-for-Test (DFT) & DFx solutions and architectures that support ATE screening, in-s...