ASIC DTCO, Timing and Technology Engineer

QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA

Engineering Group, Engineering Group > ASICS Engineering

As a DTCO and Timing Engineer, you will play a vital role in DTCO analysis targeting the Mobile, Compute, Automotive and IOT markets

• The candidate will work with best-in-class methodologies, tools and implementation flows/technologies to evaluate process technology entitlement (PPAY) for SOC products at the block/IP-level and at system-level in advanced process technologies 5nm, 4nm … 2nm and beyond (process technologies).
• Responsible for Spice simulations (Hspice/Finesim/PrimeSim/AFS/Spectre) for power and performance validation and STA sign off using PT/PT‑SI and Tempus.
• The candidate will be responsible for block level PPA analysis/implementation (RTL to GDS flow) for hard macros using FC Synthesis, FC Place and Route, Genus and Innovus.