Morgan Philips Group SA • Hsinchu, Taiwan Province, Taiwan • Posted June 02, 2026
Responsibility:
Create a performance model to enhance CPU efficiency and performance during the Pre-Silicon Stage. Scope: Consolidate the technology team for all product lines and potential future ventures. Management: Role flexibility, either as an individual contributor or a people manager, contingent on the candidate’s experience. Key skills: Performance modeling, CPU architecture, micro-architecture Requirement:
12+ years of related experience Proficiency in developing a cycle-accurate microarchitecture performance simulator for CPU core and cache subsystem, including workload and trace analysis, microarchitecture development, and correlation between RTL and performance models. Expertise in establishing microarchitecture Performance and Power modeling. Familiarity with contemporary CPU microarchitecture features like prefetch and branch prediction algorithms, uOP fusion, and more.
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