Design Engineer

ACL Digital • Mumbai, Maharashtra, India • Posted June 04, 2026

Location Mumbai, Maharashtra
Job Type Full-time
Category Engineers
Posted June 04, 2026
ASIC/DFT Engineers

Experience : 3-4 years

location : Chennai

Experience in simulation and silicon validation.

Strong expertise in DFT concepts, pattern simulation, silicon debug, and yield enhancement is required.

Hands-on experience in ATPG (coverage analysis) and memory verification, repair, and failure root-cause analysis is essential.

Experience with tools like TestKompress (ATPG), Mentor ETVerify (MBIST), and simulation tools such as VCS/ModelSim is preferred.

Scripting knowledge in Perl/Shell is a plus along with adaptability to new tools and methodologies.

Looking for candidates who can thrive in dynamic, global teams and handle multiple high-priority projects.

Apply now: [email protected]

| Notice Period: 0–15 days | Location: Chennai

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