Design Verification Engineer | ASIC Verification Engineer (UVM/SystemVerilog)
Location
Hyderabad, Telangana
Job Type
Full time
Category
Engineers
Posted
June 06, 2026
If breaking designs before tapeout sounds fun, you’re exactly who this is for.
- 4–6 years in IP/Block/Subsystem verification
- Strong expertise in SystemVerilog and UVM methodology
- Experience building test plans, environments, and testbenches
- Strong RTL debugging, assertions, and coverage analysis
- Knowledge of AXI/AHB and protocols like DDR, PCIe, NVMe
- Experience in end-to-end verification from plan to signoff
- Exposure to mentoring and working in global teams
- Strong communication and problem-solving skills
If you believe first-pass silicon is discipline, not luck, let’s connect.
Requirements
Design Verification Engineer | ASIC Verification Engineer (UVM/SystemVerilog)
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