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Design Verification Engineer/Lead

INVECAS • Hyderabad, Telangana, India • Posted June 07, 2026

Location Hyderabad, Telangana
Job Type Full-time
Category Engineers
Posted June 07, 2026

Experience

  • 4-10 years

    • Role and responsibility:

  • Strong Verification experience at Subsystem or SOC level
  • Strong in System Verilog, Verilog, UVM, C/C++, Scripting
  • Strong debugging skills, problem solving skills.
  • Good attitude , good team player with strong interpersonal skills
  • Power Management, Graphics Domain experience preferred
  • Candidate must have low power verification experience in
  • intel(ODC)/AMD(ODC) projects.

    • Academic Qualification

  • BTech / Mtech Electrical/Electronics/Computers

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