DRAM Design Tech Layout Engineer
Location
tlaquepaque, tlaquepaque
Job Type
Full-time
Category
Other-General
Posted
May 31, 2026
Job Title
JR – DRAM Design Tech Layout Engineer
Position Level: Layout/Mask Designer E3 – Relocation Level: TBD
Responsibilities- Design and develop IP layouts used in DRAM chips.
- Perform layout verification (LVS/DRC/EM), quality check and documentation.
- Deliver block‑level layouts on time with acceptable quality.
- Demonstrate leadership in planning, area/time estimation, scheduling, delegation, and execution to meet project schedules and breakthroughs in a multi‑project environment.
- Guide and lead team members in the execution of sub‑block layouts and review their work.
- Contribute to effective project management.
- Plan and detail layouts, presenting material for global teams to review.
- Collaborate with engineering teams in India, Japan, the US, and other global teams to ensure layout project success.
- BE/BTech or MTech in Electronic/VLSI Engi...