DRAM IP Layout Engineer — Precision & Leadership

Micron Technology in Tlaquepaque, Jalisco seeks a skilled engineer to design and verify layouts for DRAM products. This role involves collaborating with global teams and leading layout projects to ensure timely delivery with high quality.

Candidates should have a strong foundation in Electronic/VLSI Engineering with at least 3 years of experience in advanced CMOS processes, excellent problem-solving skills, and proficient use of Cadence tools.