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Ingeniero/a de Diseño ASIC

GMV • Tres Cantos, Comunidad de Madrid, Spain • Posted June 25, 2026

Location Tres Cantos, Comunidad de Madrid
Job Type Full-time
Category Engineers
Posted June 25, 2026

As part of the GMV Receivers team, you will have a key role in projects related to receiver technology, contributing to the development of projects and products with strong involvement in R&D activities.

You will participate in migrating an arquitecture currently implemented on Xilinx MPSoC / FPGA to an ASIC solution. Additionally, you will have the opportunity to work on the analysis of the existing design, identification of reusable blocks, adaptation of the hardware architecture, and definition of the ASIC implementation flow.

Your main tasks would be:

  • Define and evolve the target architecture for ASIC.
  • Develop and adapt RTL blocks (VHDL/Verilog/SystemVerilog).
  • Analyze and optimize internal interfaces (buses, memories, synchronization, clocks, and resets)
  • Participate in functional verification, simulation, and design debugging.
  • Contribute to the ASIC flow: synthesis, timing analysis, CDC/RDC, DFT, and design...

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