Lead PCIe RTL Engineer – Hybrid & Relocation

Hireroo is searching for a Lead PCIe Engineer located in Barcelona, Spain. The role involves defining, designing, and integrating PCIe subsystems, collaborating with various teams to deliver advanced semiconductor solutions. Candidates should have extensive experience (6+ years) in PCIe design within SoC/ASIC environments and proficiency in RTL using Verilog or VHDL. The position offers hybrid work and numerous benefits including flexible hours, medical insurance, and a relocation support package.
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