Physical Design Engineer (ASIC / AI / CPU)
Location
singapore, singapore
Job Type
Full-time
Category
Other-General
Posted
June 10, 2026
Physical Design Engineer (ASIC / AI / CPU)
Responsibilities
Lead physical design implementation for advanced-node digital ASIC, AI accelerator, and CPU chips. Perform full-chip and block-level physical design activities from gate-level netlist to GDSII tape-out, including floor planning, placement, clock tree synthesis (CTS), routing, and physical verification. Drive PPAC (Power, Performance, Area, and Cost) optimization across advanced semiconductor process technologies. Conduct layout design and optimization for both digital and mixed-signal/analog circuits. Execute signoff activities including Physical Verification (DRC/LVS), IR Drop, EM analysis, Static Timing Analysis (STA), and SPICE validation. Collaborate closely with front-end design, architecture, verification, package, and process teams to achieve design closure and product targets. Support advanced packaging initiatives and evaluate emerging technologies in heterogeneous integration, chiplet architectures, and next-ge...
Responsibilities
Lead physical design implementation for advanced-node digital ASIC, AI accelerator, and CPU chips. Perform full-chip and block-level physical design activities from gate-level netlist to GDSII tape-out, including floor planning, placement, clock tree synthesis (CTS), routing, and physical verification. Drive PPAC (Power, Performance, Area, and Cost) optimization across advanced semiconductor process technologies. Conduct layout design and optimization for both digital and mixed-signal/analog circuits. Execute signoff activities including Physical Verification (DRC/LVS), IR Drop, EM analysis, Static Timing Analysis (STA), and SPICE validation. Collaborate closely with front-end design, architecture, verification, package, and process teams to achieve design closure and product targets. Support advanced packaging initiatives and evaluate emerging technologies in heterogeneous integration, chiplet architectures, and next-ge...