Physical Design Engineer
Location
Mumbai, Maharashtra
Job Type
Full-time
Category
Engineers
Posted
June 03, 2026
Experience: 3 - 6 Years
Notice period: Immediate
Location: Bangalore & Hyderabad
Responsibilities
Mandatory Experience in
Full Chip Timing .
Strong background in
digital IC design , including floorplanning, placement, routing, clock tree synthesis, and optimization.
Tools Expertise : Proficient in
Innovus ,
ICC2 , and
Fusion Compiler
for place and route, timing closure, and physical design sign-off.
Physical Design : Experience in floorplanning, placement, routing, clock tree synthesis (CTS), and static timing analysis (STA).
Optimization : Focus on
power ,
performance , and
area (PPA)
optimization.
Sign-off : Conduct
DRC ,
LVS , and parasitic extraction for clean designs.
Advanced Process Nodes : Experience with
7nm ,
5nm , or lower process nodes.
Cross-functional Collaboration : Work closely with design, verificatio...
Notice period: Immediate
Location: Bangalore & Hyderabad
Responsibilities
Mandatory Experience in
Full Chip Timing .
Strong background in
digital IC design , including floorplanning, placement, routing, clock tree synthesis, and optimization.
Tools Expertise : Proficient in
Innovus ,
ICC2 , and
Fusion Compiler
for place and route, timing closure, and physical design sign-off.
Physical Design : Experience in floorplanning, placement, routing, clock tree synthesis (CTS), and static timing analysis (STA).
Optimization : Focus on
power ,
performance , and
area (PPA)
optimization.
Sign-off : Conduct
DRC ,
LVS , and parasitic extraction for clean designs.
Advanced Process Nodes : Experience with
7nm ,
5nm , or lower process nodes.
Cross-functional Collaboration : Work closely with design, verificatio...