Research Fellow (Semiconductor Advanced Packaging)

We are seeking a Research Fellow to advance low‑temperature Cu/dielectric hybrid bonding for fine‑pitch, high‑density interconnects by developing and validating a new flow with reliable dielectric sealing under ≤200°C. The role integrates materials selection, wafer‑level process development, and reliability demonstration to deliver a manufacturable 3D‑integration solution.

• Develop and run a Cu–Cu hybrid bonding flow for fine‑pitch 3D integration.
• Optimize process windows (pressure, temperature, anneal, surface activation) to minimize contact resistance and voids while maintaining cleanroom/tool best practices.
• Characterize materials and interfaces using optical profiling, SEM/TEM, surface chemistry, and electrical IV to translate data into process improvements.
• Validate reliability and scalability via thermal cycling, high‑temperature stress, and electrical stress on test vehicles; build prototype stacks (e.g., interpose...