Senior Analog Design Engineer
Location
Santa Clara, California
Job Type
Full-time
Category
other-general
Posted
May 14, 2026
Role: Senior Analog Design Engineer
Duration: 6-12+ Months Contract
Location: Santa Clara, CA - 5D Onsite
Must Have Skills
Skill 1 – Analog circuit design experience in DACs, ADCs, current drivers, linear regulators, and other various supporting circuitry in CMOS processes
Skill 2 – · Proficiency in the use of Python to generate test code for silicon verification & characterization
Skill 3 – Good understanding of IC device physics, spice models, ESD, latch-up, and manufacturing technology are also required
Good To have Skills –
Skill 1 – Proficient in the use of Cadence's IC design environment (Virtuoso Schematic/Layout), analog circuit simulation (Spectre/ADE), and digital RTL design (SystemVerilog).
We are looking for a hands-on senior-level engineer with good analog mixed-signal CMOS design background. In this role, you will as...
Duration: 6-12+ Months Contract
Location: Santa Clara, CA - 5D Onsite
Must Have Skills
Skill 1 – Analog circuit design experience in DACs, ADCs, current drivers, linear regulators, and other various supporting circuitry in CMOS processes
Skill 2 – · Proficiency in the use of Python to generate test code for silicon verification & characterization
Skill 3 – Good understanding of IC device physics, spice models, ESD, latch-up, and manufacturing technology are also required
Good To have Skills –
Skill 1 – Proficient in the use of Cadence's IC design environment (Virtuoso Schematic/Layout), analog circuit simulation (Spectre/ADE), and digital RTL design (SystemVerilog).
We are looking for a hands-on senior-level engineer with good analog mixed-signal CMOS design background. In this role, you will as...