Senior ASIC Design Engineer

Position Overview:

In this role, you will be part of the core team designing our next-generation AI compute engines. You will go beyond high-level RTL, diving into the fundamental hardware constraints that make high-performance AI silicon possible. You will focus on optimizing high-speed datapath logic while ensuring the design meets rigorous timing and power requirements.

Responsibilities:

• RTL Design: Implement high-efficiency logic modules using SystemVerilog/Verilog, focusing on AI-specific ALU and datapath components.
• STA & Timing: Analyze and fix timing violations (Setup/Hold) to ensure the design closes at target frequencies.
• Low Power & PPA: Apply basic low-power techniques (e.g., Clock Gating) and analyze their impact on PPA.
• Design Sign-off: Run Lint, CDC (Clock Domain Crossing), and RDC (Reset Domain Crossing) checks to ensure robust silicon behavior.