Senior ASIC Verification Engineer Role
Location
winnipeg, mb
Job Type
Full-time
Category
Other-General
Posted
June 05, 2026
Elevate your career with a leading semiconductor firm as a Senior ASIC Design Verification Engineer. Contribute your expertise in UVM and C/C++ for innovative connectivity solutions.
Our client, a newly public company, excels in purpose-built solutions for data-centric systems. We seek experienced ASIC Design Verification Engineers who have a solid foundation in verification processes using UVM and C/C++. The ideal candidate will have hands-on experience in RTL simulation and collaboration with design teams in a dynamic environment.
Key Responsibilities:
• Integrate C/C++ in System Verilog environments
• Automate verification infrastructure using Perl/Python
• Develop complex test plans and sequences in UVM
• Evaluate and debug failures collaboratively with RTL designers
• Create user-controlled random constraints in verification
Requirements:
• Bachelor's degree in Electrical Engineering (Master’s preferred)
• 2+ years supporting complex SoC products
•...
Our client, a newly public company, excels in purpose-built solutions for data-centric systems. We seek experienced ASIC Design Verification Engineers who have a solid foundation in verification processes using UVM and C/C++. The ideal candidate will have hands-on experience in RTL simulation and collaboration with design teams in a dynamic environment.
Key Responsibilities:
• Integrate C/C++ in System Verilog environments
• Automate verification infrastructure using Perl/Python
• Develop complex test plans and sequences in UVM
• Evaluate and debug failures collaboratively with RTL designers
• Create user-controlled random constraints in verification
Requirements:
• Bachelor's degree in Electrical Engineering (Master’s preferred)
• 2+ years supporting complex SoC products
•...