Senior Design Engineer
Location
hyderabad, telangana
Job Type
Full-time
Category
Other-General
Posted
June 04, 2026
RTL Design:
YoE: 4-8 Yrs
Location: Hyderabad
Notice: Immediate to 30 days
- Strong RTL design in Verilog, System Verilog
- Solid understanding of digital design fundamentals
- Familiarity with AXI/AMBA protocols
- Experience with synthesis, Lint, CDC, STA basics
- Experience in SoC integration and to communicate with the cross functional teams
- Perform global signoffs from the stake holders
- Should be good in documenting design architecture