Senior Design Verification Engineer

ASIC Verification Engineer (5–15 yrs)

• Strong in SystemVerilog & UVM testbench development (4–6+ projects)
• Experienced in IP/SoC verification, testbench architecture, and coverage closure
• Proficient in scripting (Python/Perl/Shell)
• Hands-on with tools: IUS, VCS, Questa, Verdi (debugging)
• Skilled in test plans & test case design
• Exposure to CPU-based verification (C/C++) and NoC SoCs is a plus
• Knowledge of GLS/low-power verification is a plus
• Familiar with protocols (AXI/AHB/CHI, PCIe, DDR, Ethernet, etc.)
• Strong communication, ownership, and teamwork

Location: Bangalore/Hyderabad/Noida/Chennai/Pune/Ahmedabad (Work from office)