Senior Design Verification Engineer

Job Location: Bangalore/ Hyderabad/Pune and Noida Notice Period: 15 days to 30 Days Minimum: 4 Years Key Responsibilities: Developing test plans Coding and bring up of asm, c++ tests UVM test bench components coding and maintaining Debugging regression fails Protocol: DDR,PCIE,USB,MIPI Preferred Experience: Should have worked on Processor based System or Sub-system level verification Hands on experience with assembly, UVM, SV, C++ Experience in developing complex test bench/model in UVM, Verilog, System Verilog Hands on experience in developing test plans, coverage closure Ability to code readable, maintainable and verifiable code using UVM, SV, Strong digital design concepts Experience in developing asm/C++ tests will be an added advantage Experience in Power Management, Clock, Reset will be an added advantage Experience/Knowledge DPI Interface, Ruby/Perl script programming skills will be an added advantage