Senior Design Verification Engineer
Location
Mumbai, Maharashtra
Job Type
Full-time
Category
Engineers
Posted
June 03, 2026
Hiring: PCIe Verification Engineer | Bangalore | 5+ Years
We are hiring PCIe Verification Engineers for Bangalore location with strong hands-on experience in SystemVerilog & UVM and deep understanding of PCIe protocol.
Location
Bangalore
⏳ Experience
5+ Years
Key Responsibilities
- Develop UVM-based testbench & verification environments
- Create test plans, testcases, sequences & coverage models
- Perform protocol-level verification (PCIe layers – PHY, DLL, TL)
- Debug issues using waveforms, logs & assertions
- Work on regression, coverage closure & sign-off activities
Required Skills
- Strong expertise in SystemVerilog & UVM
- Hands-on experience in PCIe (Gen3/4/5/6)
- Experience in testbench development & debugging
- Good understanding of digital design concepts
- Exposure to simulation tools (VCS / Questa / Xcelium)
Good to Have
- Experience with SoC/Sub-system...
We are hiring PCIe Verification Engineers for Bangalore location with strong hands-on experience in SystemVerilog & UVM and deep understanding of PCIe protocol.
Location
Bangalore
⏳ Experience
5+ Years
Key Responsibilities
- Develop UVM-based testbench & verification environments
- Create test plans, testcases, sequences & coverage models
- Perform protocol-level verification (PCIe layers – PHY, DLL, TL)
- Debug issues using waveforms, logs & assertions
- Work on regression, coverage closure & sign-off activities
Required Skills
- Strong expertise in SystemVerilog & UVM
- Hands-on experience in PCIe (Gen3/4/5/6)
- Experience in testbench development & debugging
- Good understanding of digital design concepts
- Exposure to simulation tools (VCS / Questa / Xcelium)
Good to Have
- Experience with SoC/Sub-system...