Senior DVT Engineer: High-Speed SerDes Validation

Celero Communications is looking for a Senior DVT Engineer in Córdoba, Argentina, to oversee the validation of cutting-edge 112G/224G interfaces critical to our Optical DSP division. The ideal candidate should have at least 5 years of experience in high-speed hardware validation, especially in the ASIC domain.

You will define test strategies and lead silicon characterization while addressing electrical impairments affecting optical performance metrics. A solid understanding of PAM4 signaling and advanced modulation techniques are essential for success in this role.