Senior Verification Engineer: Rtl/Systemverilog & Uvm
Location
estado de méxico, estado de méxico
Job Type
Full-time
Category
Other-General
Posted
June 05, 2026
Talent is seeking a skilled Senior Verification Engineer in Mexico to ensure the correctness and functionality of complex microprocessor architectures.Applicants should have over 8 years of industry experience, with strong knowledge in SystemVerilog and UVM, and the ability to collaborate closely with design teams.The ideal candidate will possess a Master's or PhD in a related field, excellent communication skills, and proficiency in scripting languages.This is a permanent position offering a negotiable salary.
#J-*****-Ljbffr