Soc Pre-Silicon Verification Engineer — Uvm/Systemverilog

Intel is seeking an experienced engineer to perform functional verification of integrated SoC designs in Guadalajara, Jalisco.
The perfect candidate will have a Bachelor's degree in related engineering fields and significant experience in verification methodologies like UVM and System Verilog.
Responsibilities include developing scalable verification plans, collaborating with design teams, and improving verification methodology.
The position requires advanced English proficiency and presents opportunity for professional growth in a dynamic environment.
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