Sr./ Lead Design Verification
Location
Bengaluru, Karnataka
Job Type
Full-time
Category
Computer Occupations
Posted
June 11, 2026
Experience: 4 to 12 Years.
Location: Bangalore.
Must have hands-on experience coding in System Verilog/UVM.
Experience developing testbenches for block level or IP level verification.
Experience working on subsystem or SoC level would be helpful.
Candidates should be proactive in communication and be able to work independently to self-manage the deliverable as per the schedules.
Developing and maintaining block level test benches.
Vplan, regression and coverage closure.
Work on testbenches with real number modeling.
Netlist and Gate level simulations.
Notice Period: 30 to 90 days
Location: Bangalore.
Must have hands-on experience coding in System Verilog/UVM.
Experience developing testbenches for block level or IP level verification.
Experience working on subsystem or SoC level would be helpful.
Candidates should be proactive in communication and be able to work independently to self-manage the deliverable as per the schedules.
Developing and maintaining block level test benches.
Vplan, regression and coverage closure.
Work on testbenches with real number modeling.
Netlist and Gate level simulations.
Notice Period: 30 to 90 days