Sr Staff Static Timing analysis (STA) Engineer
Job Description
Our team guarantee Gate netlist and SDC (Synopsys Design Constraint) qualification for Automotive SoCs. Our responsibility includes :
- RTL/Netlist qualification:
- Perform LSI ChipTop netlist check such as VC Spyglass CDC, Renesas In House Tool such as FalseCheck for asynchoronus design
- Monitor and control error judgement progress
- SDC management for each of milestone
- Hierarchical SDC creation
- IPs level constraint integration
- Delivery SDC data to other design team with high quality
- Support debugging for project members
- Monitor and control GCA (Galaxy constraint analysis) and PTE (PrimeTime error), Tempus Error/Warning judgement progress
- ECO timing
- Work with other design teams (DFT, ME/STA, BE/Layout) to develop schedule and solve problem for timing closure until TapeOut
Qualifications
- Masters or Bachelor degree in Electrical or Computer Engineering.
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