UVM and SystemVerilog Engineer at Synopsys
Location
ottawa, on
Job Type
Full-time
Category
Engineering
Posted
June 17, 2026
Become a UVM and SystemVerilog Engineer at Synopsys, specializing in verification for advanced memory interface technologies. Collaborate in a fast-paced, innovative team environment focused on quality and performance.
This role allows you to enhance your skills in a collaborative setting while contributing to the development of cutting-edge silicon solutions. You will utilize your expertise in UVM testbench implementation, functional coverage, and team mentoring to ensure high standards in product verification, all while collaborating with talented peers on design projects.
Key Responsibilities:
• Design verification test plans and coverage models
• Develop UVM testbench infrastructures efficiently
• Conduct technical reviews and ensure project clarity
• Tackle abstract verification challenges using advanced techniques
• Mentor junior engineers for skill development
Requirements:
• Expertise in SystemVerilog and UVM
• Bachelor's degree in Computer Science...
This role allows you to enhance your skills in a collaborative setting while contributing to the development of cutting-edge silicon solutions. You will utilize your expertise in UVM testbench implementation, functional coverage, and team mentoring to ensure high standards in product verification, all while collaborating with talented peers on design projects.
Key Responsibilities:
• Design verification test plans and coverage models
• Develop UVM testbench infrastructures efficiently
• Conduct technical reviews and ensure project clarity
• Tackle abstract verification challenges using advanced techniques
• Mentor junior engineers for skill development
Requirements:
• Expertise in SystemVerilog and UVM
• Bachelor's degree in Computer Science...